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文章名     作者     期刊名     摘要     卷     期         如果没有找到您所需要的文献，请点击 ——此处申请     共11条记录   A Highly Accurate Method for Assessing Reliability of Redundant Arrays of Inexpensive Disks (RAID) [作者：Elerath, JG; Pecht, M,期刊：IEEE Transactions on Computers, 页码：289-299 , 文章类型： Article，,卷期：2009年58-3] The statistical bases for current models of RAID reliability are reviewed, and a highly accurate alternative is provided and justified. This new model corrects statistical errors associated with the pervasive assumption ... Reducing Area Overhead for Error-Protecting Large L2/L3 Caches [作者：Kim, S,期刊：IEEE Transactions on Computers, 页码：300-310 , 文章类型： Article，,卷期：2009年58-3] Due to increasing concern about various errors, current processors adopt error protection mechanisms for their on-chip components. Especially, protecting caches in current processors incurs as much as 12.5 percent area o... Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures [作者：Raghavan, P; Lambrechts, A; Jayapala, M; Catthoor, F; Verkest, D,期刊：IEEE Transactions on Computers, 页码：311-321 , 文章类型： Article，,卷期：2009年58-3] Reduced energy consumption is one of the most important design goals for embedded application domains like wireless communication, multimedia, and biomedical applications. The instruction memory hierarchy has been proven... Hardware Designs for Decimal Floating-Point Addition and Related Operations [作者：Wang, LK; Schulte, MJ; Thompson, JD; Jairam, N,期刊：IEEE Transactions on Computers, 页码：322-335 , 文章类型： Article，,卷期：2009年58-3] Decimal arithmetic is often used in commercial, financial, and Internet-based applications. Due to the growing importance of decimal floating-point (DFP) arithmetic, the IEEE 754-2008 Standard for Floating-Point Arithmet... Memory MISER: Improving Main Memory Energy Efficiency in Servers [作者：Tolentino, ME; Turner, J; Cameron, KW,期刊：IEEE Transactions on Computers, 页码：336-350 , 文章类型： Article，,卷期：2009年58-3] Main memory power in volume and mid-range servers is growing as a fraction of total system power. The resulting energy consumption increases system cost and the heat produced reduces reliability. Emergent memory technolo... Cooperative Token-Ring Scheduling for Input-Queued Switches [作者：Gourgy, A; Szymanski, TH,期刊：IEEE Transactions on Computers, 页码：351-364 , 文章类型： Article，,卷期：2009年58-3] We present a novel distributed scheduling paradigm for Internet routers with input-queued (IQ) switches, called cooperative token ring (CTR), that provides significant performance improvement over existing scheduling sch... Fair Round-Robin: A Low-Complexity Packet Scheduler with Proportional and Worst-Case Fairness [作者：Yuan, X; Duan, ZH,期刊：IEEE Transactions on Computers, 页码：365-379 , 文章类型： Article，,卷期：2009年58-3] Round-robin-based packet schedulers generally have a low complexity and provide long-term fairness. The main limitation of such schemes is that they do not support short-term fairness. In this paper, we propose a new low... On the Design of Fault-Tolerant Scheduling Strategies Using Primary-Backup Approach for Computational Grids with Low Replication Costs [作者：Zheng, Q; Veeravalli, B; Tham, CK,期刊：IEEE Transactions on Computers, 页码：380-393 , 文章类型： Article，,卷期：2009年58-3] Fault-tolerant scheduling is an imperative step for large-scale computational Grid systems, as often geographically distributed nodes cooperate to execute a task. By and large, primary-backup approach is a common methodo... Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits [作者：Shi, F; Makris, Y,期刊：IEEE Transactions on Computers, 页码：394-408 , 文章类型： Article，,卷期：2009年58-3] A fast and accurate simulator with elaborate hazard detection capabilities is vital for asynchronous circuits, not only for the purpose of design validation through logic simulation, but even more importantly for the pur... Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling [作者：Goel, SK; Marinissen, EJ; Sehgal, A; Chakrabarty, K,期刊：IEEE Transactions on Computers, 页码：409-423 , 文章类型： Article，,卷期：2009年58-3] Many system-on-chip (SoC) integrated circuits today contain multiple hierarchy levels for both design and test. Hierarchy imposes constraints on the manner in which tests must be applied to "parent" cores and their "chil... On Spatial Orders and Location Codes [作者：Stocco, LJ; Schrack, G,期刊：IEEE Transactions on Computers, 页码：424-432 , 文章类型： Article，,卷期：2009年58-3] Spatial orders such as the Morton (Z) order, U-order, or X-order have applications in matrix manipulation, graphic rendering, and data encryption. It is shown that these spatial orders are single examples of entire class...