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[摘要]：Many system-on-chip (SoC) integrated circuits today contain multiple hierarchy levels for both design and test. Hierarchy imposes constraints on the manner in which tests must be applied to "parent" cores and their "child" cores. However, most prior work on wrapper design, test access mechanism (TAM) optimization, and test scheduling is hierarchy oblivious, i.e., these techniques treat all cores in an SoC as if they are at the same level of hierarchy. We first show that the test architecture, consisting of wrappers and TAMs, and the corresponding test schedule designed for nonhierarchical SoCs are not valid for SoCs with hierarchical cores. Next, we present two approaches for efficient testing of SoCs with hierarchical cores. In the first approach, the problem is solved by extending a conventional wrapper design; this approach leaves full flexibility for TAM optimization and test scheduling. The second approach is based on a modified wrapper design for parent cores that operates in two disjoint modes for testing of parent and child cores. This approach has an impact on the test architecture and corresponding schedule. We show how an existing test architecture design algorithm can be adapted for use with both approaches. Experiments with the ITC'02 SoC Test Benchmarks show that the first approach offers lower test application times, while the second approach incurs less area costs. |
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