[摘要]：We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9V, an I-ON/I-OFF ratio of 10(4). The subthreshold slope was estimated to be around 0.9V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps D-it similar to 1.2 x 10(13) cm(-2) eV(-1). Comparisons are made with both vertical Si and horizontal SiGe FETs performances. (C) 2011 American Institute of Physics. [doi:10.1063/1.3660244]
