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[摘要]：This paper presents a novel design flow for the implementation of digital systems onto SRAM-based FPGAs with soft error mitigation properties. Traditional fault detection/tolerance techniques are coupled with the device dynamic reconfiguration property to achieve soft error mitigation capabilities, and are applied to the single component, to groups of components or to the entire system, based on the most convenient trade-off with respect to a set of parameters. The design flow performs a two-steps multiobjective design space exploration, driven by a cost function taking into account resource utilization, area, and reconfiguration time. A floorplanning based on precise FPGA resource models is introduced to guarantee the feasibility of the hardened solution, identifying a convenient mapping onto the heterogeneous reconfigurable fabric. Experimental results show that the achieved solutions, aimed at achieving a prompt, "on demand" recovery when fault occurs, are characterized by a reduction in reconfiguration time that is higher than 80 percent, a significant improvement with respect to classical solutions. |
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