3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

[摘要]：parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-mu m-thick parylene-N

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