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A Reduced Complexity Wallace Multiplier Reduction

  作者 Waters, RS; Swartzlander, EE  
  选自 期刊  IEEE Transactions on Computers;  卷期  2010年59-8;  页码  1134-1137  
  关联知识点  
 

[摘要]Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexit

 
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