IEEE Transactions on Circuits and Systems II ——个性化文献订阅—

个性化文献订阅>期刊> IEEE Transactions on Circuits and Systems II


A 3 × 5-Gb/s multilane low-power 0.18-μ m CMOS pseudorandom bit sequence generator

作者	Sham, Kin-Joe (1); Bommalingaiahnapallya, Shubha (1); Ahmadi, Mahmoud Reza (1); Harjani, Ramesh (1)

选自	期刊 IEEE Transactions on Circuits and Systems II; 卷期 2008年55-5; 页码 432-436

关联知识点

[摘要]：Abstract:A low-power, three-lane, 2³¹- 1 pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-μm CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator
		被申请数（0）
[全文传递流程]：一般上传文献全文的时限在1个工作日内