A 3-8 GHz delay-locked loop with cycle jitter calibration

[摘要]：Abstract:A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correct

[全文传递流程]：

一般上传文献全文的时限在1个工作日内