[摘要]：Clock distribution is an important issue when designing Multiprocessor Systems on Chip on deep-submicron technology nodes and nonsynchronous approaches are becoming popular in this field. This work presents a lowcomplexity link microarchitecture for mesochronous on- chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speedup, power consumption reduction, and faster back- end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads. Moreover, it can be easily integrated into a conventional digital design flow since it is implemented by means of standard cells only. Results are presented by referring to the link integrated within a multiprocessor tiled architecture based on a Network- on- Chip communication backbone on a CMOS 65-nm technology.
