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[摘要]：The TLM modeling level of the SystemC language emphasizes the transactions in a complex system, considered at a very high level of abstraction. This level of specification considerably improves simulation performance and is therefore increasingly being adopted. We address assertion-based verification (ABV) of TLM SystemC models. We propose a framework for supervising during simulation the verification of temporal properties expressed in PSL. Very few modifications are needed in the original SystemC code. The TLM specification can be timed or not. The properties can involve several channels, of different types. |
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