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[摘要]：We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4-bit, 1-GS/s prototypes in 0.13-mu m and 65-nm CMOS processes, which show a small area (0.015 mm(2)) and small power consumption (< 2.4 mW). |
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