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[摘要]：We present an oscillator design method that reduces the area of LC oscillators in extremely scaled CMOS technologies by taking advantage of the high f(T) of the transistors. The oscillator is scaled to operate at a higher frequency and is followed by a fixed-ratio divider. It maintains the same power consumption and performance for a given wanted output frequency while occupying a much smaller area. In principle, by scaling up the oscillation frequency N times, a factor of 1/N-2 can be obtained in inductor area reduction. Simulated results show that with uniformly scaled inductors, the figure of merit (FoM) of the scaled oscillators at 1, 2,4, and 8 GHz can be within a I-dB difference, whereas the figure of merit normalized for area (FoMA) improves with the oscillation frequency. |
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