[摘要]：A set of graph augmentation algorithms is introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1-clock and n-clock timing faults and incorrect timer setting faults in an implementation under test (IUT). It is proven that the size of the augmented graph resulting from our augmentation algorithms is on the same order of magnitude as that of the original specification.
