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[摘要]：Planar and 3-dimensional (3D) buried-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) have been experimentally demonstrated at deep-submicron gate lengths. The effect of (NH4)(2)S passivation with different concentrations (20%, 10%, or 5%) on the off-state performance of these devices has been systematically studied. 10% (Na-4)(2)S treatment is found to yield the optimized high-k/InP harrier layer interface property, resulting in a minimum subthreshold swing (SS) lower than 100 mV/dec. Moreover, the 3D device structure greatly improves the off-state performance and facilitates enhancement-mode operation. A scaling metrics study has been carried out for 10% (NH4)(2)S treated 3D devices with gate lengths down to 100 nm, With the optimized interface passivation, 3D III-V MOSFETs are very promising for future high-speed low-power logic applications. (C) 2011 American Institute of Physics [doi:10.1063/1.3651754] |
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