[摘要]：A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18-mu m CMOS technology. The experimental result indicates that the proposed synchronous counter achieves a power saving of 64% with 15% device count reduction.
