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[摘要]：Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach. |
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