[摘要]：We present a resonant adiabatic mixed-signal 128 X 256 array processor that achieves the energy efficiency of 1.1 TMACS (10(12) multiply accumulates per second) per mW of power operating from a 1.6 V DC supply. The 1.9 mu m X 9 mu m 3T NMOS unit cell with a single-wire pitch multiplexed bit/compute line provides charge-conserving 1b-1b multiplication and single-node charge-domain analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance variability maintaining sinusoidal clock oscillations near resonance.
