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A 5-Gbit/s clock- and data-recovery circuit with 1/8-rate linear phase detector in 0.18-μm CMOS technology

  作者 Seo, Young-Suk (1); Lee, Jang-Woo (1); Kim, Hong-Jung (1); Yoo, Changsik (1); Lee, Jae-Jin (2); Jeong, Chun-Seok (2)  
  选自 期刊  IEEE Transactions on Circuits and Systems II;  卷期  2009年56-1;  页码  6-10  
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[摘要]With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-μm CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the desig

 
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