Abstract:A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-volta...
Abstract:This brief discusses the design tradeoffs for cascaded delta-sigma (ΔΣ) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and mod...
Abstract:A magnetic feedback method for enhancing the reverse isolation of low-voltage (1.2-V), single-transistor CMOS low-noise amplifiers (LNAs) is presented. The method neutralizes the gate-drain overlap capacitance o...
Abstract:In this paper, a set of CMOS differential logic circuits are introduced for use in low-power application. They perform a conditional operation for statistical power reduction during logic operation. The self-pre...
Abstract:This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35-...
Abstract:DC-DC converters under current-mode control have been known to exhibit slow-scale oscillation as a result of a Hopf-type bifurcation as one or more of the parameters of the outer voltage loop are varied. In the ...
Abstract:For Class-E1 EDGE polar transmitters, we proposed a 4-W master-slave switching amplitude modulator (MS-SAM) for both high efficiency and wide bandwidth. It consists of a combination of two step-down modules with...