- On Modulo 2(n)+1 Adder Design
[作者:Vergos, HT; Dimitrakopoulos, G,期刊:IEEE Transactions on Computers, 页码:173-186 , 文章类型: Article,,卷期:2012年61-2]
- Two architectures for modulo 2(n) + 1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2(n) + 1 addition. This sparse...
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