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文章名     作者     期刊名     摘要     卷     期         如果没有找到您所需要的文献，请点击 ——此处申请     共13条记录   The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches [作者：Qiu, XG; Dubois, M,期刊：IEEE Transactions on Computers, 页码：1585-1599 , 文章类型： Article，,卷期：2008年57-12] To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this current approach faces mounting problems as more c... Strongly Diagnosable Systems under the Comparison Diagnosis Model [作者：Hsieh, SY; Chen, YS,期刊：IEEE Transactions on Computers, 页码：1720-1725 , 文章类型： Article，,卷期：2008年57-12] A system is t-diagnosable if all faulty nodes can be identified without replacement when the number of faults does not exceed t, where t is some positive integer. Furthermore, a system is strongly t-diagnosable if it is ... Comments on "Low Diameter Interconnections for Routing in High-Performance Parallel Systems," with Connections and Extensions to Arc Coloring of Coset Graphs [作者：Xiao, WJ; Wei, WH; Chen, WD; He, MX; Parhami, B,期刊：IEEE Transactions on Computers, 页码：1726-1728 , 文章类型： Editorial Material，,卷期：2008年57-12] Recently, Melhem presented a "new" class of low-diameter interconnection (LDI) networks in this journal [10]. We note that LDI networks are the same as the previously known generalized de Bruijn graphs, point out an erro... A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems [作者：Kim, J; Lai, BC; Chang, MCF; Verbauwhede, I,期刊：IEEE Transactions on Computers, 页码：1714-U1 , 文章类型： Article，,卷期：2008年57-12] This paper presents how a multicore system can benefit from the use of a latency-aware memory bus capable of dual-concurrent data transfers on a single wire line: Source synchronous CDMA interconnect (SSCDMA-I) has been ... Automatic Generation of Modular Multipliers for FPGA Applications [作者：Beuchat, JL; Muller, JM,期刊：IEEE Transactions on Computers, 页码：1600-1613 , 文章类型： Article，,卷期：2008年57-12] Since redundant number systems allow for constant time addition, they are often at the heart of modular multipliers designed for public-key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1,0... High-Performance Mixed-Precision Linear Solver for FPGAs [作者：Sun, JQ; Peterson, GD; Storaasli, OO,期刊：IEEE Transactions on Computers, 页码：1614-1623 , 文章类型： Article，,卷期：2008年57-12] Compared to higher precision data formats, lower precision data formats result in higher performance for computationally intensive applications on FPGAs because of their lower resource cost, reduced memory bandwidth requ... The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison [作者：Bi, SQ; Gross, WJ,期刊：IEEE Transactions on Computers, 页码：1624-1632 , 文章类型： Article，,卷期：2008年57-12] The Chinese remainder theorem (CRT) and the mixed-radix conversion (MRC) are two classic theorems used to convert a residue number to its binary correspondence for a given moduli set {P-n, ... P-2, P-1}. The MRC is a wei... A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams [作者：Homma, N; Aoki, T; Higuchi, T,期刊：IEEE Transactions on Computers, 页码：1633-1646 , 文章类型： Article，,卷期：2008年57-12] This paper introduces a systematic approach to designing high-performance parallel adders based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe addition algorithms at various levels of abstraction. A high... Adaptive Fault Management of Parallel Applications for High-Performance Computing [作者：Lan, ZL; Li, YW,期刊：IEEE Transactions on Computers, 页码：1647-1660 , 文章类型： Article，,卷期：2008年57-12] As the scale of high-performance computing (HPC) continues to grow, failure resilience of parallel applications becomes crucial. In this paper, we present FT-Pro, an adaptive fault management approach that combines proac... Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems [作者：Zhuo, L; Prasanna, VK,期刊：IEEE Transactions on Computers, 页码：1661-1675 , 文章类型： Article，,卷期：2008年57-12] Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. These systems provide new opportunities for ... Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology [作者：Puente, V; Gregorio, JA; Vallejo, F; Beivide, R,期刊：IEEE Transactions on Computers, 页码：1676-1689 , 文章类型： Article，,卷期：2008年57-12] A complete mechanism for tolerating multiple failures in parallel computer systems, denoted as Immunet, is described in this paper. Immunet can be applied to arbitrary topologies, either regular or irregular, exhibiting ... Ordered Round-Robin: An Efficient Sequence Preserving Packet Scheduler [作者：Yao, JN; Guo, JN; Bhuyan, LN,期刊：IEEE Transactions on Computers, 页码：1690-1703 , 文章类型： Article，,卷期：2008年57-12] With the advent of powerful network processors (NPs) in the market, many computation-intensive tasks such as routing table lookup, classification, IPSec, and multimedia transcoding can now be accomplished more easily in ... March Test Generation Revealed [作者：Benso, A; Bosio, A; Di Carlo, S; Di Natale, G; Prinetto, P,期刊：IEEE Transactions on Computers, 页码：1704-1713 , 文章类型： Article，,卷期：2008年57-12] Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms. Among the different types of algorithms proposed for testing Sta...