- Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip
[作者:Shamshiri, S; Cheng, KT,期刊:IEEE Transactions on Computers, 页码:1246-1259 , 文章类型: 期刊论文,,卷期:2011年60-9]
- It becomes increasingly difficult to achieve a high manufacturing yield for multicore chips due to larger chip sizes, higher device densities, and greater failure rates. By adding a limited number of spare cores and wire...
- Time-Multiplexed Online Checking
[作者:Gao, M; Chang, HM; Lisherness, P; Cheng, KT,期刊:IEEE Transactions on Computers, 页码:1300-1312 , 文章类型: 期刊论文,,卷期:2011年60-9]
- There is a growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, thei...
- Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor
[作者:Karimi, N; Maniatakos, M; Jas, A; Tirumurti, C; Makris, Y,期刊:IEEE Transactions on Computers, 页码:1274-1287 , 文章类型: 期刊论文,,卷期:2011年60-9]
- We present a Concurrent Error Detection (CED) scheme for the Scheduler of a modern microprocessor. The proposed CED scheme is based on monitoring a set of invariances imposed through added hardware, violation of which si...
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