- Prefetch-Aware Memory Controllers
[作者:Lee, CJ; Mutlu, O; Narasiman, V; Patt, YN,期刊:IEEE Transactions on Computers, 页码:1406-1430 , 文章类型: Article,,卷期:2011年60-10]
- Existing DRAM controllers employ rigid, nonadaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetches the same as demand requests, and others always prioritize ...
- Two Efficient Algorithms for Linear Time Suffix Array Construction
[作者:Nong, G; Zhang, S; Chan, WH,期刊:IEEE Transactions on Computers, 页码:1471-1484 , 文章类型: Article,,卷期:2011年60-10]
- We present, in this paper, two efficient algorithms for linear time suffix array construction. These two algorithms achieve their linear time complexities, using the techniques of divide-and-conquer, and recursion. What ...
- Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
[作者:Ganguly, A; Chang, K; Deb, S; Pande, PP; Belzer, B; Teuscher, C,期刊:IEEE Transactions on Computers, 页码:1485-1502 , 文章类型: Article,,卷期:2011年60-10]
- Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm h...
- Efficient Encoding/Decoding for Second-Order Spectral-Null Codes by Reducing Random Walks
[作者:Yang, CN; Chiu, CY; Wu, GC,期刊:IEEE Transactions on Computers, 页码:1503-1509 , 文章类型: Article,,卷期:2011年60-10]
- Second-order spectral-null (2-OSN) codes are, in general, constructed from concatenating any codewords in 2-OSN code. Most 2-OSN codes adopt the Tallini-Bose random walk method in encoding and decoding, which exchanges t...
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