- A 5-Gbit/s clock- and data-recovery circuit with 1/8-rate linear phase detector in 0.18-μm CMOS technology
[作者:Seo, Young-Suk (1); Lee, Jang-Woo (1); Kim, Hong-Jung (1); Yoo, Changsik (1); Lee, Jae-Jin (2); Jeong, Chun-Seok (2) ,期刊:IEEE Transactions on Circuits and Systems II, 页码:6-10 , 文章类型: article (JA),,卷期:2009年56-1]
- With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-μm CMOS technology. The outputs of the PD have much wider pulse than those of the conve...
- Tunable linear MOS resistors uUsing quasi-floating-gate techniques
[作者:Torralba, A. (1); Luján-Martínez, C. (1); Carvajal, Roman G. (1); Galan, J. (2); Pennisi, Melita (3); Ramírez-Angulo, J. (4); López-Martín, Antonio (5) ,期刊:IEEE Transactions on Circuits and Systems II, 页码:41-45 , 文章类型: article (JA),,卷期:2009年56-1]
- Abstract:A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementati...
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